KGD Myth #1: The yield of the bare die affects the yield of the multi chip package.
KGD Myths Contents
The yield of the bare die can be considered an outcome of the test regime to which the die is subjected. It is simply a number that is reported by the automatic test equipment (ATE) upon completing the bare die tests. Yield is the number of bare die passing the test compared to the number tested. It is a number that everyone can agree on; it can be averaged over the life of the product, it can have a statistical quality when it applies to numbers of lots, and is considered highly proprietary by most IC manufacturers due to the direct relationship of yield to production cost and profit. And generally, there is no reason to disclose the yield number to customers as the only parts that are shipped have all "yielded", or passed all tests. Parts that fail to pass tests are binned out by the ATE and become scrap or parts used for yield learning.
The relevant term to customers of bare die is "defect level". Defect level is a measure of the number of die remaining in the "yielded" lot that that are actually defective and will not function correctly in the application. These defective die can be the result of test escapes. Defect levels are difficult to ascertain, and are a function of the yield of the lot and the fault coverage of the test regime used.
Figure 1: The defect level of a lot is a function of the yield reported and the fault coverage of the test program.
Unfortunately, grading a particular test program's fault coverage is not an exact science, and different electronic design automation tools (eda) that perform this task can give significantly different coverages based on the algorithm developed by the tool vendor. Therefore, there is not standardized method for reporting defect level between suppliers of bare die at present. This is a topic being discussed by IC manufacturers and eda vendors today.