Wafer Level Packaging
Flip Chip Assembly Contents
The drive to flip chip assembly is being supported by wafer level packaging approaches. Wafer-level packaging (WLP) is an advanced packaging technology in which the die terminals are manufactured and tested on the wafer, then singulated by dicing for assembly in a surface-mount line. The die terminals are characterized by wider pitch and larger ball structures than associated flip chip structures. Wider pitches are advantageous for integrating these technologies into a standard surface mount line. Larger diameter balls support the mechanical requirement to reduce TCE mismatch strain between the IC and the interconnecting substrate . Greater standoff height reduces the strain within the interconnecting structure – e.g., individual solder balls for solder based devices. Table 2 summarizes the key parameters that characterize wafer level packaged ICs.
Table 2: Comparison of wafer level package and flip chip parameters.
| Wafer Level Package | Flip Chip | |
| Pitch | 500 micron min | 125 micron |
| Pin Count | Limited | Unlimited |
| Availability | Limited Broad | Portfolio |
| Testability | Fully Tested | Fully Tested |
| Bondability | SMT Compatible | SMT-like |
| Thickness | 20 – 24 mils | 11 mils |
Wafer level packaging is a continuation of the trend to achieve the functionality and density of bare die assembly which began in the late 1990s with a series of devices known as Chip Scale Packages (CSP). Several CSP technologies have been developed by the packaging community which are very close to the dimensions of the bare silicon die. CSP technology can ease assembly and test requirements due to larger ball pitch and compatibility with traditional surface mount assembly equipment. Over the past several years, CSP pad pitches have been reducing from 1.0 to .8 to .75mm. Area array pad pitches above .5mm are considered able to be incorporated into the standard surface mount technology manufacturing flow. The wafer level packaging technologies are aimed to take advantage of the standard SMT processes while presenting the absolute minimum footprint to the interconnecting substrate. Of course, economies of batch processing that have driven the Moore’s law improvements are at work for the first time in the packaging of the device.
One strong factor in the pursuit of CSP and wafer level packaging technologies is the hope to avoid underfill. Assemblers may underfill devices because of concerns over the CTE mismatch between the silicon and the interconnecting substrate or to provide “shock” mounting of die in portable electronics that may be subjected to drops. The small die typical of the wl-csp process are less exposed to the risk of damage due to these mechanical shear forces, and the need to underfill is reduced.