System in Package (SiP) Wafer Thinning
System in Package (SiP) Assembly Contents
Stacked Package height budget
Specifications for die stacks include a maximum height of 1.2mm, and will soon be at 1.0mm, heading for 0.8mm. This requirement includes the ball height, substrate, wirebond loop height and mold cap thickness, as well as the thickness of the die and interposers.
Integrated circuits are fabricated on wafers that are originally about 350 µm thick. To be able to stack up to 8 die in packages, the wafers are first thinned to as low as 50 µm. There are four primary methods for wafer thinning: mechanical grinding, chemical mechanical polishing (CMP), wet etching and atmospheric downstream plasma (ADP) dry chemical etching (DCE). All commercially available grinding systems use a two-step process including a coarse grinding (with thinning rates of about 5 µm/sec) and a subsequent fine grinding (thinning rate =1µm/sec) [Reich ].
Handling thinned wafers is a major concern. At a 100 µm thickness, a 200 mm wafer can no longer support itself (150 µm for 300 mm wafers). Consequently, handling the thin wafers and the die (after singulation) is avoided unless absolutely necessary. The result is that companies are reluctant to do any testing or reliability screening on the die itself after singulation, putting even more focus on the KGD issue.